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93AA46/56/66
1K/2K/4K 1.8V Microwire(R) Serial EEPROM
FEATURES
* Single supply with programming operation down to 1.8V * Low power CMOS technology - 70 A typical active READ current at 1.8V - 2 A typical standby current at 1.8V * ORG pin selectable memory configuration - 128 x 8- or 64 x 16-bit organization (93AA46) - 256 x 8- or 128 x 16-bit organization (93AA56) - 512 x 8 or 256 x 16 bit organization (93AA66) * Self-timed ERASE and WRITE cycles (including auto-erase) * Automatic ERAL before WRAL * Power on/off data protection circuitry * Industry standard 3-wire serial I/O * Device status signal during ERASE/WRITE cycles * Sequential READ function * 1,000,000 E/W cycles guaranteed * Data retention > 200 years * 8-pin PDIP/SOIC (SOIC in JEDEC and EIAJ standards) * Temperature ranges supported - Commercial (C): - Industrial (I): 0C to -40C to +70C +85C
PACKAGE TYPES
DIP
CS CLK DI DO 1 8 V CC NU ORG V SS
93AA46 93AA56 93AA66
2 3 4
7 6 5
SOIC
CS CLK DI DO 1 8 V CC NU ORG V SS
93AA46 93AA56 93AA66
2 3 4
7 6 5
SOIC
NU Vcc CS CLK 1 8 ORG Vss DO DI
93AA46X 93AA56X 93AA66X
2 3 4
7 6 5
DESCRIPTION
The Microchip Technology Inc. 93AA46/56/66 are 1K, 2K and 4K low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low power non-volatile memory applications. The 93AA Series is available in standard 8-pin DIP and surface mount SOIC packages. The rotated pin-out 93AA46X/ 56X/66X are offered in the "SN" package only.
BLOCK DIAGRAM
VCC VSS
MEMORY ARRAY
ADDRESS DECODER
ADDRESS COUNTER
DATA REGISTER DI MODE DECODE LOGIC
OUTPUT BUFFER
DO
ORG CS
CLK
CLOCK GENERATOR
Microwire is a registered trademark of National Semiconductor Incorporated.
(c) 1998 Microchip Technology Inc.
DS20067H-page 1
93AA46/56/66
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings
TABLE 1-1:
Name CS CLK DI DO VSS ORG NU VCC
PIN FUNCTION TABLE
Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Memory Configuration Not Utilized Power Supply
VCC ............................................................................ 7.0V All inputs and outputs w.r.t. VSS .......... -0.6V to VCC +1.0V Storage temperature ................................-65C to +150C Ambient temp. with power applied ...........-65C to +125C Soldering temperature of leads (10 seconds)........+300C ESD protection on all pins ......................................... 4 kV
*Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2:
DC AND AC ELECTRICAL CHARACTERISTICS
VCC = +1.8V to +5.5V Commercial (C): Tamb = 0C to +70C Industrial (I): Tamb = -40C to +85C
Parameter High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current
Symbol VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 ILI ILO CIN, COUT ICC write ICC read
Min 2.0 0.7 VCC -0.3 -0.3 -- -- 2.4 VCC-0.2 -10 -10 -- -- --
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- 70
Max VCC+1 VCC+1 0.8 0.2 VCC 0.4 0.2 -- -- 10 10 7 3 1 500 100 30
Units V V V V V V V V A A pF mA mA A A A A A MHz MHz ns ns ns ns ns ns ns ns ns ns ms ms ms
Conditions VCC 2.7V VCC < 2.7V VCC 2.7V VCC < 2.7V IOL = 2.1 mA; VCC = 4.5V IOL = 100A; VCC = 1.8V IOH = -400 A; VCC = 4.5V IOH = -100 A; VCC = 1.8V VIN = 0.1V to VCC VOUT = 0.1V to VCC VIN/VOUT = 0V (Note 1 & 2) Tamb = +25C, FCLK = 1 MHz FCLK=2 MHz; VCC=5.5V (Note 2) FCLK = 2 MHz; VCC = 5.5V FCLK = 1 MHz; VCC = 3.0V FCLK = 1 MHz; VCC = 1.8V CLK = CS = 0V; VCC = 5.5V CLK = CS = 0V; VCC = 3.0V CLK = CS = 0V; VCC = 1.8V ORG, DI = VSS or VCC VCC 4.5V VCC < 4.5V
Standby current
ICCS 2
Clock frequency Clock high time Clock low time Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time Program cycle time
FCLK TCKH TCKL TCSS TCSH TCSL TDIS TDIH TPD TCZ TSV TWC TEC TWL 250 250 50 0 250 100 100
2 1
Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL = 100 pF CL = 100 pF (Note 2) CL = 100 pF ERASE/WRITE mode ERAL mode (Vcc = 5V 10%) WRAL mode (Vcc = 5V 10%)
4 8 16
400 100 500 10 15 30
Endurance
--
1M
--
1M
--
25C, Vcc = 5.0V, Block Mode (Note 3)
Note 1: This parameter is tested at Tamb = 25C and FCLK = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website.
DS20067H-page 2 (c) 1998 Microchip Technology Inc.
93AA46/56/66
TABLE 1-3:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93AA46: ORG = 1 (X 16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A5 A4 A3 A2 A1 A0 11XXXX A5 A4 A3 A2 A1 A0 10XXXX A5 A4 A3 A2 A1 A0 01XXXX 00XXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 25 9 9 9 25 25 9
TABLE 1-4:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93AA46: ORG = 0 (X 8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A6 A5 A4 A3 A2 A1 A0 11XXXXX A6 A5 A4 A3 A2 A1 A0 10XXXXX A6 A5 A4 A3 A2 A1 A0 01XXXXX 00XXXXX Data In -- -- -- -- D7 - D0 D7 - D0 -- Data Out D7 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 18 10 10 10 18 18 10
TABLE 1-5:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93AA56: ORG = 1 (X 16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address X A6 A5 A4 A3 A2 A1 A0 11XXXXXX X A6 A5 A4 A3 A2 A1 A0 10XXXXXX X A6 A5 A4 A3 A2 A1 A0 01XXXXXX 00XXXXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 27 11 11 11 27 27 11
TABLE 1-6:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93AA56: ORG = 0 (X 8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address X A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXX X A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXX X A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXX 00XXXXXXX Data In -- -- -- -- D7 - D0 D7 - D0 -- Data Out D7 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 20 12 12 12 20 20 12
TABLE 1-7:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93AA66: ORG = 1 (X 16 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXX A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXX A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXX 00XXXXXX Data In -- -- -- -- D15 - D0 D15 - D0 -- Data Out D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 27 11 11 11 27 27 11
TABLE 1-8:
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS
INSTRUCTION SET FOR 93AA66: ORG = 0 (X 8 ORGANIZATION)
SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 Address A8 A7 A6 A5 A4 A3 A2 A1 A0 11XXXXXXX A8 A7 A6 A5 A4 A3 A2 A1 A0 10XXXXXXX A8 A7 A6 A5 A4 A3 A2 A1 A0 01XXXXXXX 00XXXXXXX Data In -- -- -- -- D7 - D0 D7 - D0 -- Data Out D7 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 20 12 12 12 20 20 12
(c) 1998 Microchip Technology Inc.
DS20067H-page 3
93AA46/56/66
2.0 FUNCTIONAL DESCRIPTION
2.4 READ
When the ORG pin is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The ready/ busy status can be verified during an Erase/Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-Z state on the falling edge of the CS. The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16 bit (x16 organization) or 8 bit (x8 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially.
2.5
Erase/Write Enable and Disable (EWEN,EWDS)
2.1
START Condition
The START bit is detected by the device if CS and DI are both HIGH with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected.
The 93AA46/56/66 power up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all Erase/Write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.
2.6
ERASE
The ERASE instruction forces all data bits of the specified address to the logical "1" state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been erased and the device is ready for another instruction. The ERASE cycle takes 4 ms per word typical.
2.2
DI/DO
It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation, if A0 is a logic HIGH level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin.
2.7
WRITE
2.3
Data Protection
During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V at nominal conditions. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.
The WRITE instruction is followed by 16 bits (or by 8 bits) of data which are written into the specified address. After the last data bit is put on the DI pin, CS must be brought low before the next rising edge of the CLK clock. This falling edge of CS initiates the selftimed auto-erase and programming cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. The WRITE cycle takes 4 ms per word typical.
DS20067H-page 4
(c) 1998 Microchip Technology Inc.
93AA46/56/66
2.8 Erase All (ERAL)
The ERAL cycle takes (8 ms typical). The ERAL instruction will erase the entire memory array to the logical "1" state. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is guaranteed at 5V 10%. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete.
2.9
Write All (WRAL)
The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is guaranteed at 5V 10%. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). The WRAL cycle takes 16 ms typical.
FIGURE 2-1:
SYNCHRONOUS DATA TIMING
VIH
CS VIL VIH CLK VIL TDIS VIH DI VIL TPD DO (READ) VOH VOL TSV STATUS VALID TCZ TPD TCZ TDIH TCSS TCKH TCKL TCSH
DO VOH (PROGRAM) VOL
FIGURE 2-2:
CS
READ TIMING
TCSL
CLK
DI
1
1
0
* An
***
A0
DO
TRITRI-STATETM
0
Dx
***
D0
Dx*
***
D0
Dx*
***
D0
Tri-State is a registered trademark of National Semiconductor Incorporated.
(c) 1998 Microchip Technology Inc.
DS20067H-page 5
93AA46/56/66
FIGURE 2-3:
CS
EWEN TIMING
TCSL
CLK
DI
1
0
0
1
1
X
***
X
FIGURE 2-4:
CS
EWDS TIMING
TCSL
CLK
DI
1
0
0
0
0
X
***
X
FIGURE 2-5:
WRITE TIMING
CS
TCSL
CLK
DI
1
0
1
*A n
***
A0
Dx
***
D0
DO
TRI-STATE
BUSY
READY
TWC
DS20067H-page 6
(c) 1998 Microchip Technology Inc.
93AA46/56/66
FIGURE 2-6:
CS
WRAL TIMING
TCSL STANDBY
CLK
DI
1
0
0
0
1
X
***
X
Dx
***
D0
DO
TRI-STATE
BUSY
READY
TRI-STATE
TWL
Guaranteed at Vcc = +4.5V to +6.0V.
FIGURE 2-7:
ERASE TIMING
TCSL
CS
CHECK STATUS
STANDBY
CLK
DI
1
1
1
An
An-1 An-2
***
A0 TSV
TCZ
TRI-STATE DO
BUSY
READY
TRI-STATE
TWC
FIGURE 2-8:
CS
ERAL TIMING
TCSL CHECK STATUS STANDBY
CLK
DI
1
0
0
1
0 TCZ T SV
DO
TRI-STATE
TRI-STATE BUSY READY
TEC
* Guaranteed at VCC = 5.0V 10%.
(c) 1998 Microchip Technology Inc.
DS20067H-page 7
93AA46/56/66
3.0
3.1
PIN DESCRIPTION
Chip Select (CS)
3.4
Data Out (DO)
A HIGH level selects the device. A LOW level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought LOW during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. CS must be LOW for 250 ns minimum (TCSL) between consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status.
Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought HIGH after being LOW for minimum chip select LOW time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held LOW or HIGH during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked after the WRITE/ERASE cycle, a pullup resistor on DO is required to read the READY signal.
3.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93AAXX. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at HIGH or LOW level) and can be continued anytime with respect to clock HIGH time (TCKH) and clock LOW time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a "Don't Care" if CS is LOW (device deselected). If CS is HIGH, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a start condition the specified number of clock cycles (respectively LOW to HIGH transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (see instruction set truth table). CLK and DI then become don't care inputs waiting for a new start condition to be detected. Note: CS must go LOW between consecutive instructions.
3.5
Organization (ORG)
When ORG is connected to VCC, the (x16) memory organization is selected. When ORG is tied to VSS, the (x8) memory organization is selected. ORG can only be floated for clock speeds of 1MHz or less for the (x16) memory organization. For clock speeds greater than 1 MHz, ORG must be tied to VCC or VSS.
3.3
Data In (DI)
Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input.
DS20067H-page 8
(c) 1998 Microchip Technology Inc.
93AA46/56/66
NOTES:
(c) 1998 Microchip Technology Inc.
DS20067H-page 9
93AA46/56/66
NOTES:
DS20067H-page 10
(c) 1998 Microchip Technology Inc.
93AA46/56/66
93AA46/56/66 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices.
93AA46/56/66 -
/P
P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead SM = Plastic SOIC (207 mil Body), 8-lead (93AA46/56/66) Blank = 0C to +70C
Package:
Temperature Range:
Device
93AA46/56/66 93AA46/56/66X 93AA46T/56T/66T 93AA46XT/56XT/66XT
Microwire Serial EEPROM Microwire Serial EEPROM in alternate pinouts (SN package only) Microwire Serial EEPROM (Tape and Reel) Microwire Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com)
(c) 1998 Microchip Technology Inc.
DS20067H-page 11
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
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AMERICAS (continued)
Toronto
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ASIA/PACIFIC (continued)
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11/15/99
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Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
All rights reserved. (c) 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
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